Latent ESD Damage
Often semiconductor manufacturers are asked for the risk of their products to fail in the field due to latent ESD damage. Unfortunately, there are only a few publications on this topic, which is plausible given the difficulty to prove a latent damage.
Generally, electrical stress induced failure mechanisms, which include ESD, can be divided according to the causative quantity into:
Failures of Dielectrics due to Overvoltages
Among the dielectrics used in semiconductor technologies gate oxides respond most sensitive to overvoltages. This is due to the extremely low thickness of gate oxides, which are typically damaged by high energy (hot) charge carriers accelerated in high electric fields. These hot carriers can create local charged traps in the oxide, which may be discharged but not healed. When in the course of the time more and more hot carriers are trapped, a percolation path through the gate oxide is created until finally the gate oxide breaks down. The number of created traps depends on the thickness of the given gate oxide as well as on the magnitude and duration of the applied overvoltage. Therefore, it is generally possible, that gate oxides become subject to accelerated aging and latent damage due to ESD induced overstress.
Failures of Metal Lines due to Excessive Currents
Metal lines that become subject to excessive currents are susceptible to electromigration. Electromigration denotes the transport of metal atoms driven by a large flow of electrons in the direction of the electron flow. This can result in an accumulation of metal atoms at one end of the metal line and a vacancy at the other end of the same metal line. While the continued accumulation may lead to shorts between adjacent metal lines, increasing vacancies may finally result in a disconnected metal line. The transport of metal atoms due to electromigration depends on the material properties of the given metal line as well as on the time dependency (magnitude, polarity, duration) of the flowing current. Therefore, it is in principle possible, that metal lines become subject to accelerated aging and latent damage due to excessive ESD-induced currents.
Failures of Semiconductor Devices due to Excessive Power and Energy Dissipation
Excessive power and energy dissipation results in self-heating of semiconductor devices. As the temperature increases the intrinsic carrier density, which is crucial for the characteristics of semiconductor devices, increases. When the intrinsic carrier density exceeds the doping concentration of a given pn-junction, this pn-junction loses its blocking capability and behaves more and more like a metallic conductor. As a result, the energy dissipation increases, the semiconductor crystal heats up even more and the voltage drop across the affected part of the semiconductor decreases for a given current. Eventually, this mechanism leads to the fusing of the semiconductor and is denoted as thermal instability (thermal runaway) or second breakdown. Depending on the duration of the overstress, it may cause more or less small leakage currents which may also culminate in shorts. The excessive power or energy triggering a thermal runaway may be caused by externally enforced excessive currents and/or voltages or by triggering of instable states (e.g. snapback or oscillations).
In the past, some semiconductor manufacturers have carried out investigations, in order to assess the impact of ESD-induced "pre-damage". In these investigation no latent ESD damage was found. Of course, this does not rule out the possibility of a latent ESD damage, but it suggests that corresponding failures are very rare. The latter seems plausible considering that ESD-overstress occurs already very seldom in ESD protected areas.
In contrast, the risk of latent EOS damage has to be rated higher, since EOS includes any electrical overstress. It is therefore mandatory to read the absolute maximum ratings (AMR) of a product and to avoid a violation of its AMR under any circumstances.