esdforum.de / esd-forum.de
  • Deutsch (DE)
  • English (UK)
  • Imprint
  • Privacy Notice
  • Disclaimer
  • Info-Service
  • Contact
  • Forgot your username?
  • Forgot your password?
  • News
  • Contents
  • Association
    • Board
    • Steering Council
    • History
    • Membership
  • ESD
    • Glossary & FAQ
    • Guidelines
    • White Papers
    • Standards
    • Vocabulary
    • Abbreviations
  • Events
    • Education
    • Conferences
  • Grants
    • Jugend forscht
  • Member Area
  • Terms
  • Electrostatics
    • Charging
    • Discharge
      • Models
  • Risks
    • Components
    • PCB
    • Equipment
    • Personnel
  • ESD Control
    • Control Plan
      • Organization
      • Documentation
    • Manual Processes
      • Personnel Grounding
    • Autom. Processes
    • Packing
    • ESD Protected Area
    • Qualification
    • Verification
    • Training
  • ESD Protection
    • Protection Elements
    • Components
    • Systems
    • Simulation
      • Models
  • Metrology
    • ESD Control
    • ESD Protection
  • Guidelines
    • Components
    • Systems
    • Control Programs
  • Latch-up
    • Root Causes
    • Effects
    • Prevention
    • Verification
  • Electrical Overstress
    • Root Causes
    • Analyses
    • Prevention
  • Print
  • EOS

EOS Failure Rates

Since the early 1980s, the failure rates due to electrical overstress of all electrical failures of semiconductor devices ranges between 20% and 50%.

© 2008-2023 ESD FORUM e.V.